If you searched Superstar Sourcing for GPU Design Engineer (with 1 additional requirement) on December 21, 2025 you'd find 389 great candidates

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Staff GPU Design Engineer at Qualcomm

Perfect match - this candidate explicitly holds the Staff GPU Design Engineer title and lists RTL/Digital design skills. Staff Engineer - GPU Design at Qualcomm → Microchip Design Engineer. Excellent.

A**** A****

GPU RTL Design Engineer at Apple

Excellent fit - currently working as a dedicated GPU RTL Design Engineer, which encompasses all required skills like hardware/digital design and likely uses Verilog. GPU RTL Design Engineer at Apple → CPU Design Intern at NVIDIA. Current role is exactly what is sought. Excellent.

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ASIC Design Engineer at NVIDIA

This candidate is an excellent fit, currently leading RTL design for AVFS logic marketed for GPUs at NVIDIA, which requires deep expertise in digital design and Verilog/RTL implementation. ASIC Design Engineer at NVIDIA → Lead RTL designer for GPU-related frequency scaling logic, handling RTL implementation and behavioral models. Excellent.

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Member Of Technical Staff at AMD

This candidate is an excellent fit, having worked recently as an RTL designer on GPUs/CPUs at AMD and NVIDIA. AMD MTS → AMD Design Engineer 2 (Graphics) → NVIDIA (Graphics) → AMD Sr. Silicon Design Engineer (GPU products). Excellent.

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Hardware Design Engineer at Advanced Micro Devices

This candidate has direct, recent GPU design experience and strong hardware/digital design skills. Ex-Apple (GPU Design Engineer) → AMD (MTS) → SimpleMachines (Hardware Design Engineer), 12 years exp, focus on cache subsystems, interconnects, and silicon bring-up. Excellent.

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SoC/IP/ASIC Design Verification Engineer at Cirrus Logic

Excellent fit as this person is currently verifying Shader Core/Processor for next-gen GPUs and lists Verilog and GPU technical skills alongside ASIC Design/Verification experience. Ex-TCS → Analog Devices → Cirrus Logic → Qualcomm (GPU Shader Core Verification). Excellent.

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Staff ASIC Development/Design Engineer at Broadcom Inc.

This engineer has deep ASIC design experience including explicit mention of creating Verilog models and performing synthesis/verification phases for complex chips, making them a strong fit for the underlying engineering discipline required for GPU design. 34 years experience, ASIC Design at Intel (used Verilog, transistor design) → Tellabs → current Staff ASIC Engineer at Broadcom. Excellent.

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DRAM Digital Design Engineer

This candidate has strong digital and Verilog experience relevant to hardware design, though not explicitly GPU focused. Nanya → Micron → Nanya, 8+ years in DRAM/Rowhammer design using Verilog, gate-level design, and simulation debugging. Strong.

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Engineer

This candidate is currently working exactly on GPU power estimation at Nvidia and has explicit Verilog verification/test bench experience. Hardware Engineer → Nvidia (GPU power estimation), ASIC/Verilog verification experience. Excellent.

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Senior Principal Engineer at RF Integration Inc.

This seems like a very strong fit as the candidate explicitly designed and simulated an LSI ASIC based 2D GPU recently. Sr. Principal Engineer, recent work on RF ASIC testing, older role designing/simulating 2D GPU, managed ASIC design/verification flow. Excellent.

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Senior Engineer at Doble Engineering Company

This candidate has extensive experience across the hardware design cycle, explicitly mentioning Verilog RTL design. Ex-AMD, Trebia, Doble, with 35 years experience. Excellent.

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Senior Staff ASIC Design at Marvell Semiconductor

This candidate is a high-level ASIC design engineer whose recent work involves complete SOC development, integration, RTL, and interface to backend teams, directly matching the digital hardware engineering required for GPU design. Staff/Sr Staff ASIC Design at Zoran/Marvell, leading SOC integration/RTL/DFT/timing closure. Excellent.

J*** B****

This individual has direct experience designing high-speed IOs for GPUs at NVIDIA, making them an excellent match for a GPU Design Engineer role, despite the mixed-signal focus. GPU/Chipset IO design/validation → Mixed Signal Design/Verification at NVIDIA (long tenure) → RfStream. Excellent.

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Sr. RTL Performance Engineer at NVIDIA

Excellent fit with recent, strong RTL/ASIC performance engineering roles at NVIDIA, which strongly implies GPU/high-performance hardware design. Ex-Intel PD → NVIDIA Sr RTL Performance Engineer, 8.2 total years. Excellent.

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MTS Silicon Design Engineer at AMD

Currently a Silicon Design Engineer at AMD with explicit Verilog and digital design skills, making them a strong candidate for a related GPU role. AMD → Synaptics → Sony, strong background in Digital/Silicon Design with Verilog expertise. Strong.

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Looking for Full-time opportunities | GPU DV @AMD | MSEE @SJSU | Cadence

This candidate has direct, recent experience verifying GPU micro-architecture, strongly implying overlap with hardware design principles, and likely uses Verilog/SystemVerilog. GPU Verification Engineer @ AMD → DV Engineer @ Cadence → DV Engineer @ Apple → DV Engineer @ Cadence → Intern. Excellent.

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ASIC Engineer

Excellent background in ASIC engineering at NVIDIA, explicitly interested in GPGPU architecture, and skilled in Verilog, fitting the requirement closely despite not having 'GPU Design Engineer' in the title. Background: ASIC Engineer at Blink → ASIC Engineer at NVIDIA (twice) → ASIC Engineer at Google. Strong interest in GPGPU architecture. Strong.

S**** M****

ASIC Design Engineer at Cisco | MSEE USC 23

This individual has strong digital and hardware design background explicitly mentioning Verilog skills in an ASIC context. GPU specific experience is the only missing piece for a perfect score. EE @ USC → Digital Design Intern → ASIC Design Engineer at Cisco. Excellent.

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Silicon Digital Design Engineer, Google LLC

This individual is currently an RTL Design Engineer at Google working on silicon digital design, showing strong technical relevance. Current role at Google → Intel SOC Design, 10 years experience. Strong.

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GPU DV @ Apple | Masters in Computer Engineering Texas A&M University | RVCE’22

This candidate clearly targets GPU DV at Apple, has strong technical skills including Verilog/System Verilog, and interests in RTL Design, making them an excellent match for verification heavy roles adjacent to design, though qualification is MS level. Strong current focus on high-end silicon verification. Qualcomm Intern → current Masters, 2 years experience. Strong.

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RTL Design Engineer | Seeking full-time opportunities in Hardware/VLSI Design

This candidate has strong foundational skills for RTL/digital design, including Verilog, which aligns well with GPU engineering requirements. Ex-Arm → Microchip Technology, MS in VLSI. Excellent.

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Principal RTL Design Engineer at Arm

Excellent fit - Principal RTL Design Engineer at Arm with extensive experience in ASIC design/verification, architecture, and explicitly lists Verilog/RTL Design expertise. → Intel → Samsung → Arm Principal. Excellent.

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GPU Design Verification Engineer at AMD

This candidate has direct recent experience as a GPU Design Verification Engineer at AMD, strongly implying deep knowledge of GPU architecture and related hardware/digital design principles, even if the role isn't pure design, Verilog overlap is highly likely in this domain. Silicon Labs → Redpine Signals → AMD. Excellent.

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MTS ASIC Design & Verification

Excellent match due to recent experience verifying RTL for mobile processors and explicitly mentioning GPU verification at AMD, showing direct alignment with the domain, though the role is verification/design hybrid. AMD ASIC Design & Verification (41 years total) → verified RTL for GPUs, mobile processors using Verilog. Excellent.

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RTL Design @Google

This candidate is an RTL designer specializing in ML accelerators using FPGAs, which is extremely close in mindset and required skills (RTL development for high-performance parallel processing) to GPU design, including HLS and RTL kernel work. PhD holder, RTL Design @Google (ML accelerators, HLS/RTL kernels mentioned). Excellent.

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Member Of Technical Staff Silicon Design Engineer at AMD Ex: Intel - Senior ASIC IP Logic design Eng.

This engineer has deep ASIC/FPGA logic design experience and explicitly mentions Verilog/SystemVerilog expertise, indicating strong relevance for GPU design work. Ex-Intel → AMD, 15+ years specialization in front end logic design/RTL using SystemVerilog/Verilog. Excellent.

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Senior ASIC Engineer @NVIDIA | NCSU | BITS Pilani

This candidate has significant direct experience in GPU memory architecture and ASIC roles which strongly aligns with GPU Design Engineering. Ex-NVIDIA → current NVIDIA, experience in thermal modeling and verification, some mention of hardware/ASIC focus. Strong.

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ASIC Design Engineer

This candidate has extensive experience in front-end RTL design, which forms the basis of GPU digital design, and explicitly lists Verilog skills. Ex-Intel → Marvell → Innovium, focusing on ASIC design/verification. Strong.

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Engineer at Apple

This candidate explicitly looked for GPU architecture roles previously, has strong ASIC/RTL experience, and lists Verilog. Engineer at Apple (6+ years) → ASIC design intern at NVIDIA, lists Verilog, Architecture skills, and sought CPU/GPU roles. Strong.

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Qualcomm | Nvidia | Qualcomm | MS CE @NC State | Qualcomm | NIT Calicut 2019

This candidate has relevant ASIC design experience and mentions Verilog skills. ASIC RTL Design engineer with 3 years experience. Qualcomm → NVIDIA → Qualcomm, MS CE @NC State. Strong.